1. Field of the Invention
This invention relates to digital logic circuits and, more particularly, to logic circuits having level-sensitive latched outputs.
2. Description of Related Art
Logic gates such as NAND and NOR gates are well known for generating output signals representing logical combinations of the states of input signals. Many ways for implementing there logic gates are known. Pseudo-nMOS logic gates illustrate one implementation. FIG. 1 shows a block diagram of a conventional pseudo-nMOS logic gate 100 that can be fabricated using a CMOS process. Logic gate 100 receives a plurality of binary input signals X1 to XN and generates a binary output signal Z representing a logical combination of the states of input signals X1 to XN. Logic gate 100 includes a current source 120 which acts as a pull-up device and a pull-down network 110 (typically constructed from n-channel MOSFETs). Current source 120 is typically constructed using a p-channel MOSFET having a source connected to a supply voltage VDD, a drain connected to an output terminal 130 of logic gate 100, and a gate connected to a reference voltage VSS (ground potential). Pull-down network 110 is constructed so that when a desired logical combination of the states of input signals X1 to XN is "false" or a binary "0", pull-down network 110 shorts output terminal 130 to reference voltage VSS. This pulls output signal Z down to binary "0" or "false". When the desired logical combination of the input states is "true" or a binary "1", no complete path through pull-down network 110 conducts a current; and current source 120 pulls output signal Z up to a binary "1" or "true".
An advantage of pseudo-nMOS logic gate 100 is that a relatively simple and straight forward transistor network 110 can pull down output signal Z when desired for a complex logic function. A disadvantage of pseudo-nMOS logic gate 100 is the power dissipation caused by the current through pull-down network 110 when output signal Z is stable at a binary "0". Because of this current, pseudo-nMOS logic gates typically consume more power than other CMOS gates and may require special attention to ensure that the pseudo-nMOS gate have an adequate power supply. The static power consumption may make pseudo-nMOS logic gates unsuited for low-power circuits.
Another disadvantage of pseudo-nMOS logic gate 100 is that output signal Z when at binary "0" is above reference voltage VSS; and if the output of pseudo-nMOS logic gate 100 is connected to the input of a CMOS gate, the binary "0" state voltage level may cause the CMOS gate to dissipate power even when inputs are unchanging. Since CMOS gates usually dissipate power only when inputs are switching, the dissipation of power when inputs are stable may be unexpected and undesirable. This discourages mixing pseudo-nMOS logic gates and CMOS circuits.
Latches are another well known type of digital circuit. FIG. 2 shows the block diagram of a level-sensitive latch 200. Latch 200 consists of switches 240 and 270 and inverters 250 and 260 and operates in two modes, flow-through mode and latched mode. In flow-through mode, switch 240 is closed (i.e. conducts) and switch 270 is open (i.e. does not conduct), so that an input data signal D is applied to an input node 282 of inverter 250. In flow-through mode, an inverted output signal Q from inverter 250 is the logical complement of input data signal D, and an output signal Q from inverter 260 has the same binary state as input signal D. In latched mode, data switch 240 is open to disconnect input signal D from node 282 and data switch 270 is closed to short node 284 to node 282. In latched mode, output signals Q and Q retain the logic states from when latch 200 entered latched mode. Typically, switches 240 and 270 are transmission gates controlled by an enable signal. When the enable signal has one binary state, latch 200 is in flow-through mode; and when the enable signal has the other binary state, latch 200 is in latched mode.